1. Introduction

a CPLD (Complex Programmable Logic Device) It is a digital device that allows to program the logic functions to be implemented within the same device.

It is an evolution of prior programmable logic devices such as PAL and GAL (for more information see who) . A further evolution of the CPLD is represented by FPGA (for more information see who) much more powerful and complex than CPLD, and they typically require an external memory for storing the configuration.

The fundamental element of the CPLD is the macrocella, which constitutes the atomic logic element.

In the case of the family of Max II of Altera devices (now Intel), the atomic element is called LE (Logic Element) and it differs from the classical macrocella the GAL (product of terms such as AND-OR):

Wanting to simplify, an LE is constituted by a LUT (Look Up Table) with 4 inputs and by a Flip-Flop. The LUT can be regarded as a kind of “PROM decoding”, programming it is possible to realize a logic function at will within the LUT. The Flip-Flop constitutes an atomic memory element which can be associated with the logical function of the LUT (to realize, and example, logs, counters, etc.).

Within a EPM240T100 type CPLD we're going to use are 240 The, in addition there is an EEPROM memory block that holds the configuration to be loaded at power (CFM), and a further user EEPROM memory block (UFM).

The CPLD programming is to load the configuration (also known as bitstream) within the EEPROM and CFM, if used, within the FOM.

2. What do you need to begin

Hours we will see that “ingredients” They need to start using the CPLD EPM240T100 representing “entry level” Max II family.

2.1 The CPLD board

Of course, first of all you need a card “development” which contains a CPLD EPM240T100. To this end you can use the CPLD Fun Board I made for this purpose, or another business card containing a EPM240T100 CPLD or another of the same family.

Without going to choose expensive cards (> 100$) like this:

you can orient on a card of this type:

or even this:

which can be purchased from known e-commerce sites from around 6$.

2.2 The MCU card (optional)

Normally the economic trading cards, compared to CPLD Fun Board, They lack some “peripherals” come led, buttons, display a 7 segments, etc. and not have to use as a microcontroller “generator of stimuli”. Consequently it will be necessary to connect external devices using, eg, a breadboard, and finding an additional card with a microcontroller.

In this regard I note that the CPLD operates at 3.3V, so it is not easy to use as a common MCU board Arduino Uno (since it operates at 5V), but it is good to move towards cards with 3.3V MCU.

I recommend using a card “Maple Mini” that uses an ARM Cortex M3 MCU 32 type bit STM32F103, which it is the same used in the CPLD Fun Board, and that can be programmed with the IDE Arduino. In this way you can use the same sketch, taking care to make any small adjustments in the case of the connections should be different:

Usual, a “Maple Mini” It can be purchased on known sites from around 3/4$.

Of course you can also choose any other MCU like the PIC, provided operating at 3.3V. Obviously in this case you can not use “sketch” examples, but you have to make their own.

2.3 The USB Blaster programmer

To perform the upload of the configuration inside the CPLD is necessary to use an appropriate programmer called USB Blaster. This programmer is readily available on the usual sites from around 3$ and the flat cable is normally included in 10 conductors:

 

 

2.4 The fourth l'ide 2

Finally, you must download and install the Quartus II IDE. In the following I will use the version 13.0.SP1, because I need to maintain this version for another project using a Cyclone II FPGA (It is the latest version that supports that FPGA). If you want you can try to use the latest version (is currently the 17) which still supports the Max II series, but it is possible that the screenshots do not coincide used below.

To download the version you can use this 13.0.SP1 link. E’ You need to create an account to proceed to download. I recommend you select the tag “Combined Files” and download about 4.4GB file with everything you need.

3. Configuring the Quartus II

As I mentioned earlier, All screenshots refer to 13.0.SP1 version of the IDE.

In addition the suggested configuration is referred to CPLD Fun Board, but it is also recommended for any other development board used.

From the main menu select Quartus II “File” -> “New Project Wizard…“:

then “Next >“:

and insert the name of the project folder you want to create. In the example we will write “test1” for all fields as screenshots. E’ Note that Quartus II It does not like names with interior spaces.

Then we go on with “Next >“:

to still “Next >“:

Now in “Family” select MAX II, in the field “Package” select “TQFP” and in the field “Available devices” the line “EP240T100C5“.

Then we go on and on with “Next >“:

it's still “Next >“:

and finally click on “Finish“. Now we have an empty template and you can change the configuration.

From the main menu select Quartus II “Assignments” -> “Devices…“:

and click on the button “Device and Pin Options…“:

and select “Enable device-wide reset (DEV_CLRn)” e “Enable device-wide output enable (DEV_OE)“. This will be enabled functions “DEV_CLRn” e “DEV_OE” the CPLD board Fun Board.

These are two important functions: the first resets the flip-flop of all LE (Logic Elements) with the key “DEV_CLRn”, and the second enables the ability to force all of the pins of I / O of the CPLD in high impedance through switch “DEV_OE”.

We now set the status of the CPLD pin unused. With the term unused It means not explicitly referenced in the programming phase.

From the same window, select the left “Unused Pins“:

and select in the field “Reserve all unused pins” the option “As input tri-stated weak pull-up“. This is the best configuration, and more “safety” per la CPLD Fun Board, but it is also recommended in general.

Now is the chance to save the project, which will be used below for the first example of use, the ubiquitous flashing LED…

4. A classic project to start: the flashing LED

As has been the tradition of the first sample project will be to do a flashing LED.

In the following I will continue to refer to the CPLD Fun Board, but the content is however also applicable to other tabs having the foresight to modify the physical pin with respect to the HW configuration of the card used.

Furthermore, to make it even easier to understand, It will use the environment “schematic entry” and libraries that allow you to simulate the behavior of HW well-known family of digital integrated circuits 7400. Therefore it will not make any mention of the use of HDL languages ​​like VHDL, requiring know-how specific.

This tutorial will use as a starting point the project test1 previously saved, going to realize a configuration that the CPLD, starting from a clock of 36MHz input, He divides it with a chain of dividers to obtain a frequency of approximately 2Hz. This last will be used to flash an LED. The clock of 36MHz will be produced with the STM32F103 aboard the CPLD Fun Board.

In case of using a commercial card, simply select input the oscillator to 50MHz which normally equips said cards. The frequency will be produced in this case by about 3 Hz.

4.1 Edit Project

Open the previously saved project from the main menu of Quartus II “File” -> “Open Project…” and select the file “test1.qfp”. Note that the extension .qfp It is used to project files Quartus II:

Then from the main window:

We create a new file for the wiring diagram to realize.

From the main menu select Quartus II “File” -> “New…“:

and then “Block Diagram/Schematic File“. This will create a new file .bdf:

Now we have to draw the schematic of what we want to achieve within the CPLD.

We will use three counters 74393 as room dividers 1:256.

Then select the icon “Symbol Tool” from the editor toolbar:

and write 74393 in the field “Name“:

press the button “OK” and we place three counters 74393 in sheet using the left mouse button:

Then we press the button (physical) “ESC” and we select the icon “Orthogonal Node Tool” to make connections:

and we complete all as shown here:

Now the key again “ESC” and the riselezioniamo “Symbol Tool“, then write”not” in the field “Name“:

posizioniamo and two NOT gates as shown here:

 

Now we add an input pin (il clock) and an output (lED). In addition we will also add an additional input pin for a Fun Board CPLD button that will connect to the signal “Clear” common to the three 74393.

After pressing the button (physical) “ESC” we select the “Pin Tool” and the sub-selection “Input“:

and we posizioniamo two input ports as follows:

and an output port for selecting the LED “Pin Tool” and then “Output“:

posizioniamo and the exit door as shown here:

Now for greater clarity we rename the gates of input / output (pin_name1, …3) as shown below, double-clicking on each name to be changed:

At this point, the editing is complete, and it is appropriate to save it.

4.2 Assignment of the physical pin

Now you need to associate the input / output ports of the various physical CPLD pin. But before you precede should use a little trick to make the next steps easier. In fact, however, we must now make a compilation the entire project, in this way they will automatically be available on the Pin Planner the port names we used in schematic editor in the previous step. Having to do with devices 100 and the pin is not a trivial matter…

In this regard, we click on the icon “Compilation“:

and we await the completion of the compilation:

If we did everything right, They do not have to appear errors, but any warning that ignore.

Now press the button “OK” and click on the icon of the “Pin Planner“:

the window will be activated Pin Planner:

This is the place to associate the physical pins to the door of the electric scheme, and which define the electrical parameters (logic levels, eventuali pull-up, etc..).

Now we begin to associate with the physical pin using the field “Location” in the bottom of the window:

To assign the physical pin must click the intersection of the gate line to be associated with the column Location. In the case of CPLD Fun Board from the circuit diagram shows that the clock input pin (dal pin 29 MCO of STM32F103) It is connected to the pin 14 the CPLD, similarly the LED LED1 is connected to the pin 50 and USR4 key is connected to the pin 54 the CPLD.

If you are using a different card you will need to make the necessary changes.

You will end:

Now you need to make some adjustments to some default parameters of some physical pins that take into account the HW of the CPLD board Fun Board.

First is the case of activating the internal resistance of the pin pull-up 14 (clock) since in certain conditions the output of the STM32 MCO is in high impedance. This can prevent states “floating“.

To do this we select “On” by column “Weak Pull-Up Resistor” (NOTE: whether in your installation do not appear certain columns, go with the mouse on any title of a column and press the right button. At this point the selected column to be added to the current view):

Then it is necessary to take into account that the USR4 button is connected to an analog circuit for de-bouncing, Consequently, it must be activated one Schmitt Trigger input to pin 54:

we can close the window at this point of the Pin Planner (You do not need to save anything explicitly). Now you need to make a new compilation of the project as before:

and it is good practice to check that all the pins assigned post-compilation are correct. To do so we click on the folder “Fitter“:

then the folder “Resource selection“:

and then click the item “All Package Pins“:

Now you can check that all the pins correspond to the expected.

4.3 USB Blaster Connection Procedure

At this point we're ready to upload. But first you must connect the USB Blaster programmer following the procedure laid down in its downloadable manual who.

The steps to follow are the order:

1. verify that the target (the card with CPLD) is not powered;
2. connect the USB Blaster programmer for the first USB PC (It will thus be fed from the PC);
3. connect the flat cable to JTAG 10 conductors to target;
4. feed target. If the Fun Board CPLD This results in connecting the card's USB connector to a second USB port on your PC.

In the following video we are shown all the steps as per procedure:

4.4 the CPLD programming

From the main window to the icon of the Quartus II “Programmer“:

You will see the Programmer window:

at this point perform the following steps:

• verify that the USB controller is selected Blaster (1);
• if you do not press the button “Hardware Setup…” (2) and select it;
• press the button “Auto Detect” (3) and verify that do not contain errors;
• verify that all the check “Program/Configure and “Verify” (4) are selected;
• press the button “Start” (5) to start programming.

Wait for the program.

4.5 How to disconnect the USB Blaster

If you wish to disconnect the USB Blaster programmer you need to follow the steps in the manual.

The steps to follow are the order:

1. disconnect the power supply of the target. If the Fun Board CPLD this means unplug the USB cable from the card;
2. disconnect the flat connector 10 conductors (JTAG) from the card;
3. disconnect the USB Blaster from the USB connector.

In the following video we are shown all the steps as per procedure:

4.6 Sketch for the generation of the clock at 36MHz

We previously said that it is necessary to generate a clock to give input to the CPLD. To do this we will use the MCU STM32F103 aboard the CPLD Fun Board.

In case of using another tab, you will have to do in order to bring / to generate a clock signal to the CPLD.

Without going into the details of the hardware inside of STM32F103, we will use the MCO that if suitably programmed pin allows to bring the outside a clock derived from the system's internal clock:

The sketch that activates the pin MCO is as follows:

---

void setup() {
// put your setup code here, to run once:

// Set the MCO pin to output the clock to the CPLD (GCLK1 pin 14). See STM32F103 Reference Manual RM0008
RCC_BASE->CFGR = RCC_BASE->CFGR | 0x07000000; // Set MCO[2:0] = 111 (inside RCC_CFGR register) for 36MHz clock output
GPIOA->regs->CRH = GPIOA->regs->CRH | 0x00000003; // Set output mode on PA8 @ max freq 50MHz (MODE8[1:0] = 11)
GPIOA->regs->CRH = GPIOA->regs->CRH & 0xFFFFFFF3; // Set output mode on PA8 as general push-pull output (cnf8[1:0] = 00)
GPIOA->regs->CRH = GPIOA->regs->CRH | 0x00000008; // Set output mode on PA8 as alternate push-pull output (cnf8[1:0] = 10)

}

void loop() {
// put your main code here, to run repeatedly:

}

---

The end result is shown in the following video :

Note that pressing the Reset button (reset of the MCU) the LED stops flashing for a while, since, during the reset and subsequent reboot ceases the clock signal, until the bootloader relinquishes control to the user program which reactivates the.

You can also see the effect of DEV_CLRn button that resets all flip-flops inside the CPLD, making clear the counters configured in the same CPLD. Pressing the button USR4 the counters of Clear signal switches, obtaining the same effect.

Activating the switch DEV_OE are forced into high impedance across the pin I / O of the CPLD, with consequent interruption of the flashing.

5. References to deepen

• Manuale in Quartus II V13.1 who;
• Max II Device Handbook who;
• Datasheet MCU STM32F103 who;
• Reference Manual RM0008 (MCU STM32F103) who;

VOTE