The field-effect transistor is a semiconductor device unipolar three-terminal that has very similar characteristics to those of their counterparts bipolar transistors. Eg, high efficiency, instant operation, robust and economical and can be used in most applications of electronic circuits to replace their cousins BJT.
The field-effect transistor can be made much smaller than a BJT transistor equivalent and, together with their low power consumption and minimum power dissipation, make them ideal for use in integrated circuits such as CMOS range of digital logic chips.
We know that there are two types of bipolar transistors, NPN e PNP, they basically describe the physical arrangement of the doping of P-type or N that characterize them. This also applies FET there are two basic classifications for Field Effect Transistor, FET calls N-channel and P-channel FET.
The field-effect transistor is a three-terminal device constructed without PN junctions within the path of the main current between the terminals Drain and Source. These terminals correspond respectively to the collector and the emitter of the bipolar transistor. The path of the current between these two terminals is called “channel” which can be constituted by a P-type semiconductor material or N-type.
The control of the current flowing in this channel is obtained by varying the voltage applied to the Gate. As their name suggests, bipolar transistors are devices “bipolar” because they operate with both types of charge carriers, holes and electrons. The field-effect transistor, on the other hand, It is a device “unipolar” that depends only on the electron conduction (channel N) a gap (P-channel).
The DONEIt has an advantage over its cousins standard BJT, since the input impedance (also) she is very tall (thousands of Ohm and beyond), while the BJT is relatively low. This high input impedance makes them very sensitive to input voltage signals, but the price of this high sensitivity also means they can be easily damaged by static.
There are two families of transistors field effect, the field-effect transistor in junction O JFET and the transistor to the gate of field effect isolated O IGFET, more commonly known as field-effect transistor semiconductor metal oxide O MOSFET.
The transistor junction field effect
We know that a BJT is constructed using two PN junctions in the path of the main current between the emitter terminal and the collector. The transistors of junction field effect (JUGFET the JFET) It has no PN junctions but has instead a narrow piece of semiconductor material which forms a high resistivity “channel” N-type or P-type slide for the majority carriers with two connections at the two ends were called respectively Drain e Source.
The N-channel JFET have a higher channel conductivity (lower resistance) compared to their types of P equivalent channels, because the electrons have a higher mobility through a conductor with respect to the gaps. This makes the N-channel JFET a more efficient conductor than the P-channel counterparts.
Within this channel there is a third electrical connection that is the gate terminal call it forms a PN junction with the main channel.
Comparison of connections between a JFET and BJT
basic structure for both JFET configurations.
The “channel” semiconductor transistor junction field effect is a resistive path through which a voltage VDS It makes a current flow ID and therefore the JFET can conduct current equally well in both directions. Since the channel is resistive nature, a voltage gradient is then formed along the length of the channel with which this voltage becomes less positive as we go from the DRAIN terminal to the SOURCE terminal.
The result is that the PN junction has therefore a high reverse bias on the D terminal and a lower reverse bias on the terminal S. This distortion causes the formation of a “depletion layer” inside the channel and the width of which increases with the bias.
The magnitude of the current flowing through the channel between the Drain and Source terminals is controlled by a voltage applied to the Gate terminal, that is polarized inversely. In an N-channel JFET to this gate voltage is negative while for a P-channel JFET the Gate voltage is positive.
The main difference between JFET and a BJT device is that when the junction is reverse biased JFET, the Gate current is practically zero, while the current of the BJT base is always a value greater than zero.
Biasing of an N-channel JFET N
The cross-sectional diagram above shows an N-channel type semiconductor with a region of P called the Gate type diffused in the N-channel type that forms a PN junction is inversely polarized and it is this that forms the junction depletion region around the area of the Gate when external voltages are not applied. The JFET are therefore known as depletion mode devices.
This depletion region produces a gradient that is of variable thickness around the PN junction and limits the current flow through the channel reducing its effective width and thereby increasing the overall strength of the same channel.
So we can see that the most impoverished part of the depletion region is located between Gate and Drain, while the area is not emptied between Gate and Source. Thus the JFET channel leads with zero bias voltage applied (that is, the depletion region has a width close to zero).
No external voltage of the gate (VG= 0) and a small voltage (VDS) applied between G and S, the maximum saturation current (IDSS) It will flow through the channel only limited by the small region of emptying around the junctions.
If a small negative voltage (-VGS) It is now applied to the gate, the size of the depletion region starts to increase while reducing the overall effective area of the channel and thereby reducing the current flowing . Then, applying a reverse bias voltage increases the width of the depletion region which in turn reduces the conduction of the channel.
Since the PN junction is reverse biased, little current will flow in gate.Dato connection that the gate voltage (-VGS) It is made more negative, the channel width decreases until it flows more current between Drain and Source and the FET is said “pinch-off” (similar to the cut-off region for a BJT). The voltage at which the channel is closed is called “shutdown voltage” (VP).
JFET Channel pinch off
In this pinch-off region of the Gate voltage VGS controls the channel current and VDS has little or no effect.
The result is that the FET acts more like a voltage controlled resistor which has zero resistance when VGS = 0 and maximum resistance “ON” (RDS) when the gate voltage is very negative. Under normal operating conditions, the gate JFET is always negatively oriented with respect to the source. It is essential that the gate voltage is never positive because if it happens all the channel current will flow toward the gate damaging the JFET.
The transistor junction field effect P-channel works exactly like the N channel above, with inverted polarization.
The output characteristics of an N-channel JFET N:
Since a JFET is a voltage controlled device, “no current flows in the gate!”.
The example of the characteristic curves shown above shows the four different regions of operation for a JFET and these are given as:
Ohmic Region – When VGS = 0 the channel depletion layer is very small and the JFET acts as a voltage controlled resistor.
interruption Region – the JFET acts as an open circuit because the resistance of the channel is at its maximum.
Saturation or active region- The JFET becomes a good conductor and is controlled by VGS voltage while the voltage VDS has little or no effect.
Breakdown Region – The VDS is high enough to cause the interruption of the resistive channel of the JFET and exceeding the maximum uncontrolled current.
The characteristic curves for a transistor channel junction field effect P are the same as the previous ones, except that the voltages have opposite sign.
the resistance of the channel is given as:
Resistance of the drain-source channel.
Dove: gm is the “gain transconductance” since the JFET is a voltage controlled device and that represents the current rate of change with respect to change in the Drain Gate-Source voltage.
As the bipolar junction transistor, the field-effect transistor being a three-terminal device is capable of three distinct operating modes and can therefore be connected to the inside of a circuit in one of the following configurations.
Common Configuration Source (CS)
In the configuration Common Source (similarly common emitter), the input is applied to the gate and its output is taken as shown Drain. This is the most common mode of operation of the FET because of its high input impedance and good amplification of voltage and as such amplifiers Common Source are widely used.
This mode is generally used audio frequency amplifiers and pre-amplifiers and stadiums high input impedance. Being an amplifier circuit, the output signal is “out of phase” with the entrance.
Common Gate Configuration (CG)
In the configuration Common Gate (similar to the common base), the input is applied in S and its output is taken into D with the gate connected directly to ground (0v) as shown. The high impedance input of the previous connection is lost in this configuration since the common port has low input impedance, but a high impedance output.
This type of FET configuration is used in high-frequency circuits or impedance matching circuits if low input impedance must be adapted to an impedance of high output. The output is “in phase” con l’input.
Configurazione Common Drain (CD)
In the configuration Common Drain (similar to the common collectore), the input is applied to the gate and its output is taken from S. The common drain configuration or “source follower” It has an impedance of high input impedance and low output and a nearly unitary voltage gain, It is then used in buffer amplifiers. The voltage of the configuration of the source follower gain is less than unity and the output signal is “in phase” with the input signal. The output is in phase with the input.
The JFET amplifier
Just as the bipolar junction transistor, the JFET can be used to realize class amplifier circuits A single-stage with the JFET common source amplifier and the characteristics are very similar to the common emitter circuit BJT. The main advantage that the JFET amplifiers have on BJT amplifiers is their high input impedance that is controlled by the resistive network of gate bias formed by R1 and R2 as shown.
This amplifier circuit common source (CS) It is biased to work in the classroom “A” from the network voltage divider formed by the resistors R1 and R2. The voltage across the resistor RS is generally set to about a quarter diVDD, (VDD/ 4) but can take any arbitrary value.
The gate voltage required can then be calculated starting from this value RS. Because the gate current is zero, (IG= 0), it is possible to set the rest of DC voltage required by the proper choice of resistors R1 and R2 .
With this I leave for the moment not to stretch the article too, as soon as possible speak diffusely of insulated gate FET thereby completing this topic.