This is a later article on the basic configuration of the DC / DC converters as does the configuration title is called SEPIC has its salient data summarized in two factors:
absence of direct connection between input and output thanks to the presence of a capacitor
operation in buck-boost mode.
It will be described the usual areas in which it is used and an example with all the formulas to calculate a real power supply with such a configuration.
Lithium-ion batteries and low-ESR capacitors are giving a new splendor to the SEPIC topology. a SEPIC (converter single-ended primary inductance) It is distinguished by the fact that its input voltage range may overlap to the output voltage. Since the literature on SEPIC is poor, designers with little experience of energy converters avoid resorting to this configuration, it is time to do some’ clarity.
Lithium batteries are very successful, thanks largely to their impressive energy density. A single lithium cell provides a voltage of 4,2 V when it is fully charged can replace 3 No celle NiCd NiMH. This voltage depends on the remaining capacity it can be used up to the voltage of 2,7 V. A SEPIC is an ideal circuit for using such batteries.
The SEPIC also find application in TV of modern power supplies to raise the starting voltage from 315V to 400V for their property to generate low noise on the electricity network. It also provides the output level required even if the peak input voltage is higher (reduction in the percentage of faults from electrical events).
Boost topology (Figure 1) It is the basis for the SEPIC converter. The principle of the boost converter I clarified it in a previous article:
1° the switch Sw is closed during TON, increasing the magnetic energy stored in the inductor L1.
Figure 1. This boost topology is the basis for the power supply circuits SEPIC.
2° the switch opens during TOFF, offering D1 and COUT as the only path for the magnetic energy stored. COUT filters the pulse generated from L1 through D1. When VOUT is relatively low, it is possible to improve the efficiency by using a Schottky diode with low forward voltage. VOUT must be greater than VIN. In the opposite case (WINE> VOUT) D1 is polarized directly and nothing prevents the current flow from VIN to VOUT.
The SEPIC scheme Figure 2 removes this limitation by inserting a capacitor (Cp) between L1 and D1. This obviously capacitor blocks any DC component between the input and the output. The anode of D1, however, It must connect to a known potential. This is achieved by connecting D1 to ground through a second inductor (L2).
Figure 2. An advantage of the SEPIC circuit, in addition to buck properties / boost, It is a capacitor (Cp) that prevents unwanted current flow from VIN and inOUT.
L2 can be separated from L1 or wrapped on the same core, depending on the needs of the application. Since the latter configuration is simply a transformer, one could argue that this is a classic flyback. The absence of a network of typical flyback snubber proves otherwise. The leakage inductance is not a problem in the SEPIC schemes. The main parasitic resistances RL1, RL2, RSW and Rcp are associated to L1 respectively, L2, SW and Cp.
Although it has very few elements, the operation of a SEPIC converter is not so simple to be abstracted in equations.
Suppose that the ripple current and voltage values are small compared to the DC components.
To start, We express the fact that at equilibrium there is no DC voltage drop between the two inductances L1 and L2 (neglecting that of the parasitic resistances). Therefore, Cp sees a DC potential VIN on the one hand, through L1, and land on the other side, through L2. The DC voltage of Cp is:
(VCp)VIN = (Eq. 1)
“T” It is the period of a switching cycle. We will call α the portion of T for which Sw is closed and 1-α the remaining part of the period.
Since the average voltage on L1 is equal to zero during steady state conditions, the view voltage from L1 during αT (Your) It is exactly offset by the observed tension during (1-a) T (Toff):
αTVIN = (1-a) T (VOUT+ VD+ VCp- WINE) = (1-a) T (ARCH + VD).
VD is the forward voltage drop of D1 for a continuous stream of (il1 + IL2), e
VCP is equal to VIN:
(ARCH + VD) / VIN = α / (1-a) Ai = (Eq. 2)
Ai is called amplification factor, dove “i” It represents the ideal case for which the parasitic resistances are null. Neglecting VD than VOUT (as a first approximation), we see that the relationship between VOUT and VIN can be greater or less than 1, depending on the value of α (with equality obtained for α = 0.5).
This report presents the characteristics of SEPIC converters than classologie stepdown or classic stepdown.
The more precise expression Aa explains the parasitic resistances in the circuit:
This formula is used to calculate the minimum amplification factors, typical and maximum VIN(faithful, Aarip e Aamax). The formula is recursive (“A” It appears in both result in the expression), but some iterative calculations lead to the solution asymptotically. The expression neglects transition losses due to the switch Sw and the reverse current in D1. These losses are generally negligible, especially if Sw is a fast MOSFET and its drain voltage excursion (VIN + ARCH + VD) It remains below 30V (the apparent limit for low-loss MOSFET today).
In some cases, you must also take into account losses due to reverse current D1 and core losses due to high-level induction gradients. You can extrapolate from the corresponding values of α’ Eq.2:
αzz = Aazz / (1 + Aazz), where zz is min, typ o max. (Eq. 4)
The DC current through Cp is nothing, then the average output current can only be provided by L2:
IOUT= IL2 (Eq. 5)
The L2 power dissipation requirement is attenuated, since the average current in L2 is always equal to IOUT and does not depend on variations in VIN. To calculate the current in L1 (il1), we assume that no current can flow through Cp. Therefore, the charge coulomb flowing during αT is perfectly balanced by a charge of opposite coulomb during (1-a) T.
When the switch is closed (for an interval αT) the potential of the node A is set at 0V. According to equation 1, the potential of the node B is -Vin, that inversely reverses D1. The current through Cp is then IL2.
When the switch is open during (1-a) T, IL2 flows through D1 while IL1 flowing through Cp: αT * IL2 = (1-a) T * IL1.Sapendo that IL2 = IOUT,
IL1 = Aazz*IOUT (Eq 6)
Since the input power is equal to the output power divided by the efficiency, IL-1 is highly dependent on VIN. For a given output power, IL1 increases if VIN decreases. Knowing that IL2 (then IOUT) flows into Cp during αT, We choose Cp so that its ripple ΔVCp is a very small fraction of Vcp (by γ = 1% al 5%). The worst case occurs when VIN is minimal.
Cp> IOUT*αminT / (c * VINmin) (Eq. 7)
The combination of the operation of the high frequency controller and the recent progress in multilayer ceramic capacitors (MLC) allows the use of small and non-polarized capacitors Cp. Ensure that Cp is able to support the PCP power dissipation due to its internal resistance (Rcp):
Pcp = Aamin*Rcp * IOUT² (Eq. 8)
RSW, usually constituted by the drain-source resistance MOSFET switch in series with a shunt for limiting the maximum current, It involves the following loss:
Psw = Aamin (1 + faithful) Rsw IOUT² (Eq. 9) The losses Pr1 and Pr2 due to internal resistances L1 and L2 are easily calculated :
Prl1 = Aamin² Rl1 IOUT² (Eq. 10)
Prl2 = RL2 IOUT² (Eq. 11)
When calculating the loss due to D1, pay attention to evaluate VD to the tune of IL1 + IL2:
PD1 = VD× IOUT (Eq 12)
L1 is selected so that its total current ripple (DIL1) is a fraction (b = 20% al 50%) The IL1. The worst case for β occurs when VIN is maximum, because DIL1 is maximum when IL1 is minimal.
Assuming β = 0,5:
L1min = 2 T (1-αmax) VINmax/ IOUT (Eq. 13)
Choose a standard value close to that calculated for L1 and make sure that its saturation current satisfies the following conditions:
If L1 and L2 are wound on the same core, you have to choose the larger of two values. A single core obliges the two windings to obtain the same number of turns and then the same inductance values. Otherwise, the tensions between the two windings will be different and Cp will act as a short circuit to the difference. If the voltages of the windings are identical, generate the same current and cumulative gradients. Therefore, the natural inductance of each winding should be equal to only half of the calculated value for L1 and L2.
Since between the two windings there is a large potential difference, you can save on costs by wrapping them together in the same operation. If the cross-sections of the windings are equivalent, the resistive losses differ because their current (IL-1 and IL-2) differ. The total loss, however, It is lower when the losses are evenly distributed between the two windings, so it is useful to set the cross section of each winding according to the current carrying. This is especially easy to do when the windings are made up of multiple strands to contrast the skin effect. Finally, the size of the core is chosen to accommodate a much greater saturation current of (il1 + IL2 + DIL1) the highest expected internal temperature.
The purpose of the output capacitor (COST) It is the average of the current pulses supplied by D1 during Toff. The current transitions are brutal, then COUT should be a high-performance component such as that used in a flyback topology. Fortunately, ceramic capacitors today provide a low ESR. The minimum value for COUT is determined by the amount of ripple (ΔVOUT) that can be tolerated:
COST> = Aamin IOUT αmin T / ΔVOUT (Eq. 17)
The value of a real output capacitor may need to be much larger, especially if the load current is composed of high-energy pulses. The input capacitor can be very small, thanks to the filtering properties of the SEPIC topology. Usually, CIN can be ten times smaller than COUT:
CIN = COST / 10 (Eq. 18)
After this long series of formulas we move to design a real circuit, supplying a power LEDs with three lithium cells inserie. initial data:
VINmin = 8,1 V
VINtyp = 11,1 V
VINmax = 12,6 V
VOUT = 11,7V
IOUT = 2 A
T = 2μS
MD = 0,42 V
A round of initial estimates provides the following approximate values:
L1 e L2 = 22μH,
RL1 = RL2 = 39mΩ,
Rcp = 50mΩ
Rsw = 35mΩ.
Diagram of a SEPIC power supply 24 W con LM3478
Using the’equation 2
(ARCH + VD) / VIN = α / (1-a) Ai =
for first thing they calculate the ideal amplification factors Ai corresponding to the minimum VIN, typical and maximum as 1,568, 1,144 e 0,968. Using these values in’Equation 3
get the most accurate values Aazz 1.735, 1.292 e 0.88 respectively. The corresponding duty cycles are derived from’equation 4
αzz = Aazz / (1 + Aazz), where zz is min, typ o max.
come 0,611, 0,533 e 0,492.
L2 corrente (IL2) 2A is equal to the second’equation 5
IL1 and varies according to VIN. Using the’equation 6
IL1 = Aazz*IOUT
We get IL1 values 3,136A, 2,288A and 1,936A as VIN varies from minimum to maximum.
We get a minimum value of Cp 3,5μF staring γ = 4% nell’equation 7
Cp> IOUT*αminT / (c * VINmin)
The nominal voltage of Cp is deducted from’equation 1
If the input voltage should not exceed 12V, a ceramic capacitor rated at 16V 10uF should go. Modern MLC capacitors easily meet the expected Rcp of 50 M: and easily support the power loss of 400 mW deducted from’equation 8.
Pcp = Aamin*Rcp * IOUT²
The following parameters are calculated in the worst case, that is minimal VIN:
A switch from 33 M: must dissipate 500 mW according to the’equation 9,
Psw = Aamin (1 + faithful) Rsw IOUT²
that allows you to choose an external transistor in a container SOT223.
The equations 10 e 11
Prl1 = Aamin² Rl1 IOUT²
Prl2 = RL2 IOUT²
damage losses 380 MW e 156 mW for L1 and L2. We verify here that the copper section of L1 should be greater than that of L2.
Using the’equation 12
PD1 = VD× IOUT
D1 to calculate the power loss 0,84 W, we see that D1 is the main source of loss. It is therefore important to choose an efficient rectifier, if not a synchronous rectifier.
per L1, l’equation 13
L1min = 2 T (1-αmax) VINmax/ IOUT
It suggests a minimum value of 9,8μH, which it is close to the estimated value of 22μH. For normal operation with a L1 value of 22μH , l’equation 14
It provides a peak current of 3,14 A . A device with a rating of 5A provides a reasonable margin. Ensure that D1 can sustain high temperature current pulses equal to IL1 + IOUT= 5,2 A and an average current IOUT = 2A.
Similarly, l’equation 15
L2min = 2 TαmaxVINmax/ IOUT
It leads to a minimum value L2 of 12,4 μH. Once again, 22uH is a reasonable value. According to’equation 16
He says that the output capacitor should be at least 33μF(33) .
CIN = COST / 10
3,3μF says that should be enough for CIN.
It remains to describe only the three typical components of the integrated LM3478 used for supply management R1, R2 and R3 together with the resistor to pin 7.
R1 and R2 so as to form a subsequent block triggers the transistor until the voltage at pin divider for the output voltage control 3 drops below 1.25V
R3 on the need for a short-circuit current protection flowing in L1, the values, the limit is set at about 8A
The resistance to the pin 7 fixing the frequency of oscillation, the value refers to a total period of 2US which equates to a frequency of 500KHz.
As can be seen it is not a simple design of a SEPIC but the final results are surprising in terms of size and circuit simplicity. In case you want to use a single core for both inductors goes halved the value of the inductance of the individual windings.
Fundamental for the operation is that the two coils have identical value otherwise the diode breaks coming less the average value of initial assumptions null in the two inductances.
With this I leave in the hope of being of help to someone who is interested in this circuit