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After having made some cards based on the back-CPU coupling + After having made some cards based on the back-CPU coupling Z80-MBC2, the V20-MBC and the 68After having made some cards based on the back-CPU coupling, After having made some cards based on the back-CPU coupling + After having made some cards based on the back-CPU coupling.
After having made some cards based on the back-CPU coupling (is. After having made some cards based on the back-CPU coupling). After having made some cards based on the back-CPU coupling.
After having made some cards based on the back-CPU coupling Studio 68 After having made some cards based on the back-CPU coupling 68000 (68After having made some cards based on the back-CPU coupling) After having made some cards based on the back-CPU coupling. E’ After having made some cards based on the back-CPU coupling (GPIO) After having made some cards based on the back-CPU coupling “After having made some cards based on the back-CPU coupling” After having made some cards based on the back-CPU coupling (is. After having made some cards based on the back-CPU coupling).
In addition, I also added an MCU (In addition, I also added an MCU) come “In addition, I also added an MCU” In addition, I also added an MCU (In addition, I also added an MCU) In addition, I also added an MCU “In addition, I also added an MCU” (In addition, I also added an MCU).
E’ In addition, I also added an MCU (In addition, I also added an MCU 16 bit) In addition, I also added an MCU.In addition, I also added an MCU 68 In addition, I also added an MCU, In addition, I also added an MCU.
In addition, I also added an MCU 68000 In addition, I also added an MCU “In addition, I also added an MCU” In addition, I also added an MCU 68 come “In addition, I also added an MCU”. In addition, I also added an MCU “In addition, I also added an MCU” In addition, I also added an MCU “clone” In addition, I also added an MCU.
In addition, I also added an MCU:
< In addition, I also added an MCU…>
In addition, I also added an MCU 0402 on both sides of the PCB.
The “on both sides of the PCB” on both sides of the PCB:
on both sides of the PCB 1: on both sides of the PCB (on both sides of the PCB “on both sides of the PCB”);
on both sides of the PCB 2: pulp;
on both sides of the PCB 3: on both sides of the PCB + on both sides of the PCB (on both sides of the PCB “on both sides of the PCB” on both sides of the PCB);
on both sides of the PCB 4: on both sides of the PCB (on both sides of the PCB “on both sides of the PCB”).on both sides of the PCB, on both sides of the PCB “ratnest”:
on both sides of the PCB:
on both sides of the PCB…
on both sides of the PCB @Picmicro675 on both sides of the PCB:
on both sides of the PCB.
on both sides of the PCB “on both sides of the PCB” 🙂 :
In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary “In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary” In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary “In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary” In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary. In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary, In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary “In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary” In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary (In the previous image you can see a portion of the mass layer alone in which I highlighted some groups of holes in red which, due to the necessary).
To date, I have managed to mount about 80% of the PCB:
This includes the power supply, the USB port and related circuitry, the FPGA and related programming circuitry, the STM32 MCU complete with SD (bottom side) and related programming circuitry from USB and DRAM (SDR type). The latter is one of the most difficult parts to test because it requires having a suitable controller in the FPGA, in addition to an interface that allows the STM32 to be able to read and write access to the SDRAM asynchronously through the local LCB2 bus (see block diagram in the first post), and finally a SW to run in the STM32 as a RAM tester.
To speed up I used a “core” open source in VHDL that I found “around”, while I necessarily created the asynchronous access interface to the DRAM by the STM32 (in VHDL) and the relative testing SW as specific to this card.
The STM32 section of the Studio tab 68 it is compatible with the development board Discovery di ST and there is also a suitable circuitry which allows to use the internal serial bootloader of the STM32 “commanded” Arduino IDE (after loading the “core” officer of ST):
In this way it is possible to use Arduino IDE to quickly build and load test SW (obviously this does not prevent the use of any development system for STM32 through the SWD programming / debugging port which is still present).
I am currently testing the DRAM and if the result is positive I will be able to move on to the next step which will be the assembly and test of the 68SEC000 CPU…
I try that for me such a project would be like going to the moon. I am amazed by the great capacity you have.
@Picmicro675: Thanks too good… 🙂
I added the 68SEC000 CPU and started the first simple test programs written in assembler 68000 and using the internal RAM of the FPGA (M4K blocks) which allows you to preload the image of a binary file inside the “bitstream” sent with the JTAG:
To run the tests I am using 3 toolchain in “parallel”. The first is for sources 68000 in assembler and the production of a binary file in .mif format.
The second is the Quartus IDE for the synthesis of the VHDL and the predisposition of the preloaded RAM with the binary file in machine code 68000.
The third is the Arduino IDE with the “core” for the STM32 to be able to program the STM32 MCU that acts as “bridge” between the FPGA and the USB.
At this point I have to start thinking about how to test the external bus, and I will probably need a suitable additional card…
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